1. Field of the Invention
The present invention relates to a clock regeneration circuit which inputs a multi-level input signal, with at least two signal levels, and outputs a clock signal synchronized with a period of the multi-level input signal.
2. Description of the Related Art
Heretofore, a clock regeneration circuit that inputs a two-level signal and outputs a clock signal synchronized with a period of the two-level signal has been proposed (see, for example, Japanese Utility Model Application Laid-Open (JP-U) No. 5-70044). FIG. 1 is a block diagram schematically showing structure of a conventional clock regeneration circuit. In the clock regeneration circuit shown in FIG. 1, a half-bit delay device 11 delays a two-level signal inputted at an input terminal by a duration corresponding to half of a one-bit length, and an exclusive-OR (XOR) circuit 12 calculates XOR values of the inputted two-level signal and a two-level signal that is outputted from the half-bit delay device 11. A band-pass filter (BPF) 13 extracts a bit rate base frequency component from output of the XOR circuit 12, and thus regenerates a clock signal which is synchronized with a period of the two-level input signal.
For the conventional clock regeneration circuit described above, the input signal is assumed to be a two-level NRZ signal. However, if a multi-level input signal with three or more signal levels were to be inputted to the above-described conventional clock regeneration circuit, the following problem would arise.
For an n-level signal taking n signal levels (n being an integer of at least 3), there are (n−1) ranges in which a threshold can be set—between 0 and 1, between 1 and 2, . . . , or between (n−1) and n. If a threshold value of the XOR circuit 12 is set to one of the above-mentioned (n−1) ranges, edges of the multi-level input signal that can be detected are limited to edges that cross the specified single threshold. Therefore, electrical power of the signal outputted from the XOR circuit 12 is greatly reduced, and consequently electrical power of the clock signal outputted from the BPF 13 is also smaller. Therefore, if a multi-level signal were to be inputted to the conventional clock regeneration circuit, the clock signal would be very susceptible to the effects of external noise, and quality of the clock signal would fall.